Multiprocessor parallel computing systems have recently become available which may be coupled to a host computer to enhance its performance. Generally, an attached parallel processing system of this type has a relatively limited instruction set. It is designed to perform simple, repetitive operations in parallel and, so, reduce the elapsed time for processing a program. A system of this type is generally coupled to a communications bus of the host computer and is treated as an input/output (I/O) device.
The most common types of attached multiprocessor systems are the Multiple-Instruction Multiple Data (MIMD) systems and the Single-Instruction Multiple Data (SIMD) systems. An MIMD system is a conventional multiprocessor system where each processor may execute a separate program operating on a separate data set. The processors in a system of this type may perform separate tasks or they may each perform a different sub-task of a common main task.
In an SIMD system, each processor may have a different set of data in its associated memory, but all processors are governed by a common controller, and perform the same operations on each of the different data sets. Processors of this type may be used, for example, for simulation programs in which the effects of a stimulus on a set of points spanning an area or a volume are calculated simultaneously.
When either of these two types of systems is coupled to a host computer, instructions and data are transferred between the multiprocessor system and the host computer via a communications bus.
Many computer systems include apparatus which continually checks the validity of the data being processed. This apparatus ranges from parity checking circuitry to circuitry which inserts and analyzes error correcting codes (ECC's). Although apparatus of this type may be used to maintain data integrity separately in the host computer and in the multiprocessor system, it may be difficult to verify the integrity of data transferred between the two systems.
To illustrate how these problems may occur, consider an exemplary multiprocessor system, the Polymorphic-Torus network, which is described in a paper by H. Li et al. entitled "Polymorphic-Torus Network" Proc. Int. Conference on Parallel Processing, PP 411-414, 1987, hereby incorporated by reference. This system is an SIMD processor network in which N.sup.2 bit-serial processors are arranged in an N.times.N matrix. Assuming the host computer uses K-bit words in its data processing, data values are transferred to the multiprocessor system in groups of N.sup.2 K-bit words. In a typical application, these data values may be stored into a buffer as N.sup.2 K-bit words and may be shifted out of the buffer into the N.sup.2 bit-serial processors as K N.sup.2 -bit words. Any ECC incorporated in the K-bit words generated by the host would be difficult to use in the attached multiprocessors. Similarly, any ECC developed by the multiprocessors would be difficult to use in the host processor.
An SIMD multiprocessor system may be used in a multiprogramming environment, that is to say, the system may run multiple programs on a time-slice basis. For example, when a program running on the multiprocessor system enters a wait state, e.g. to perform an I/O operation, another program may be activated to run on the system. When this second program enters a wait state, the first program is reactivated. Operating the system in this manner is generally more efficient than restricting it to execute each program to completion before starting the next program. However, there is a potential for data corruption if one program is allowed access to data locations used by another program while the other program is inactive.
U.S. Pat. No. 4,773,038 to Hillis et al. relates to an SIMD system in which each memory associated with one of the processing elements may be subdivided. Each processing element operates on the contents of each subdivision sequentially to simulate a greater number of processors.
U.S. Pat. No. 4,727,474 to Batcher relates to a multiprocessor system which has a staging memory system that includes error detection and correction apparatus for data used by the multiprocessor system.
U.S. Pat. No. 4,636,942 to Chen et al. relates to a computer system that has multiple independent processors. The system includes a set of shared registers which are used to coordinate access to resources that are common to all of the processors.
U.S. Pat. No. 4,569,052 to Cohn et al. relates to apparatus for protecting computer memory which uses a parity matrix to generate an error correcting code.
U.S. Pat. No. 4,523,273 to Adams, III et al. relates to a multistage data routing system which includes error correction and error detection apparatus.
U.S. Pat. No. 4,299,790 to Gilliand et al. relates to a MIMD system which includes apparatus for checking memory accesses against base and length parameters for a task. If an attempted access is found to be out of range, the task is suspended. Data transfers between asynchronous tasks are facilitated by semaphores implemented in hardware.
U.S. Pat. No. 4,101,960 to Stokes et al. relates to an SIMD computer system which includes apparatus that contains bounds and descriptions of vectors defined in a memory space. Memory access errors may be checked by this apparatus to provide early detection of errors in vector processing.